The increasing complexity on chip and of chip designs is inducing more defects in System on Chip (SoC) designs, and these defects are causing an increase in the testing requirements for each chip.
The yield of SOC and their designs is directly linked to the memories on the SOC because there are around 60 to 70 percent of the memories on the chip. Thus, the memory yield is directly converted to or related to the chip yield. A robust design and a very well controlled process can reduce the defect level in the memory, but, unfortunately in the newer technologies, as the gate lengths shrink, the defect level goes beyond the control of process and of the design as well.
Typically, the interfaces which are being used to test the memory in the current methodologies add a lot on the input of the memory as well because they do not penetrate much inside the memory hierarchy to increase the observability. As result, the conventional memory interface circuits are additional overheads to the memory. They add some extra timing overhead as well. Further, as these interfaces are not embedded inside the memory, it adds on to the cost of plugging it with the memory and increase the difficulty of measuring the timing defects between the system flip flops. It is therefore very difficult to predict whether the fault is in the memory or is at the interface.
U.S. Pat. No. 6,044,481 illustrates a conventional interface for testing memories. The interface includes a plurality of programmable input pins and output pins besides a logic interface or component used for connecting external signals to the plurality of programmable input and output pins. The external signals are processed by the logic interface and then communicated to a plurality of memory connection pins that couple to the memory device. This logic component is capable of being configured in accordance with one or more memory testing methodologies including a serial built-in-self-test (BIST), a parallel built-in-self-test (BIST), a parallel test, a serial test, and a scan test. The configuring is performed by interconnecting selected ones of the plurality of input pins and output pins to the external signals that drive the logic interface in a test mode that operates in one or more memory testing methodologies or a mission mode. The testing techniques disclosed by the aforementioned patent do not take into account area constraints for a typical SOC design.
Further, the conventional interfaces, which are being used to test the memory in the current methodologies, add a lot on the input of the memory, and they do not penetrate much inside the memory hierarchy to increase the observability. The memory interfaces, which have been proposed and are being used lack several desirable properties. For example, in case of a multiple memory structure in a chip, the interface may add on to the complexity by adding multiple test interface structure.